1. Field of the Invention
The present invention relates generally to integrated circuit implementations of high-speed amplifiers, and more particularly to a preferred implementation of a collector resistor in a high-speed amplifier integrated circuit.
2. Description of the Related Art
FIG. 1 is a schematic diagram of a conventional high-speed cascode amplifier having a push-pull output stage. The circuit asserts amplified output potential Vout in response to input potential Vin, when biased by bias potential Vb (when supply voltage Vcc is applied across its top and bottom rail). The amplifier of FIG. 1 is typically implemented as an integrated circuit (or portion of an integrated circuit), with some or all of its resistors comprising layers of polysilicon over a layer of field oxide (with a substrate of P-type semiconductor material under the field oxide layer). Such an integrated circuit implementation will be assumed in the following description.
In FIG. 1, resistor R.sub.c is connected between nodes X and Y. Node X is coupled to the top rail, which is at potential Vcc. Node Y is coupled to the base of transistor X83, to the collector of transistor X84, and to one end of resistor R22. The circuit has a capacitance (e.g., 5 femtofarads) between node Y and the bottom rail (which is at ground potential), which capacitance is represented by capacitor C145 (shown in phantom view).
The gain of the amplifier of FIG. 1 is determined by the resistance ratio -R.sub.c /R.sub.e, where R.sub.e is the equivalent overall resistance connected between the emitter of transistor X91 and the bottom rail. The resistance of gain-setting resistor R.sub.c is typically 3400 Ohms, as indicated in FIG. 1. Resistor R.sub.c typically comprises a polysilicon strip (or multiple polysilicon strips connected in series) over a layer of field oxide, with a substrate of P-type semiconductor material under the field oxide layer.
A limitation of the amplifier of FIG. 1 is that the stray capacitance of polysilicon resistor R.sub.c (over the field oxide on which it is formed) slows down the circuit's output transient response. Thus, the absolute value of the amplifier's gain is necessarily reduced in order to achieve faster transient response (by implementing resistor R.sub.c with reduced resistance)
FIG. 2 is a schematic diagram of a high-speed cascode amplifier which differs from the FIG. 1 amplifier only in that polysilicon resistor R.sub.c is implemented in an improved manner, in order to reduce its stray capacitance over the field oxide on which it is formed, and thus to improve the amplifier's output transient response without reducing the absolute value of its gain. Resistor R.sub.c of the FIG. 2 circuit can be implemented in accordance with the invention (over multiple tubs of semiconductor material), in a manner to be described below with reference to FIGS. 9, 10, and 11.
Alternatively (and not in accordance with the present invention), if the FIG. 2 circuit is implemented over a substrate of P-type semiconductor material, resistor R.sub.c of the FIG. 2 circuit is implemented over a single tub of N-type semiconductor material which is formed in the substrate as shown in FIGS. 3 and 4. This "one-tub" implementation is inferior to the inventive "multiple-tub" implementation of resistor R.sub.c in several respects to be explained below, but it does represent an improvement over the FIG. 1 implementation.
In the implementation of FIGS. 3 and 4, resistor R.sub.c of FIG. 2 comprises ten series-connected strips of polysilicon RS1-RS10. Strips RS1-RS10 are connected in series, with metal connector M6 connecting strips RS1 and RS2, metal connector M7 connecting strips RS2 and RS3, metal connector M8 connecting strips RS3 and RS4, metal connector M9 connecting strips RS4 and RS5, metal connector M10 connecting strips RS5 and RS6, metal connector M11 connecting strips RS6 and RS7, metal connector M12 connecting strips RS7 and RS8, metal connector M13 connecting strips RS8 and RS9, and metal connector M14 connecting strips RS9 and RS10. Metal contact M15 is coupled to node Y (of FIG. 2). Metal contact M5 is coupled through metal contacts M4, M3, and M2 to metal contact M1, and contact M1 is coupled to node X (of FIG. 2).
The implementation of resistor R.sub.c shown in FIGS. 3 and 4 (and the embodiment of FIG. 2 which includes this implementation of R.sub.c) is manufactured on a substrate 10 of P-type semiconductor material. On substrate 10, a layer 11 of N-type semiconductor material (denoted as an N+ buried layer in FIG. 4) is formed (such as by implanting N-type impurities in a rectangular region of the substrate material, and then removing unwanted portions of the N-type semiconductor material). Layer 11 has uniform (relatively small) thickness, except that it has relatively large thickness at one portion underlying metal contact M16 (so that layer 11 extends all the way up to contact M16 as shown in FIG. 4). Thus, N-type semiconductor layer 11 has a rectangular periphery as shown in FIG. 3.
After layer 11 has been formed on substrate 10, epitaxial layer 12 of N-type semiconductor material is grown over layer 11 (except for the thick portion of layer 11 which extends up to contact M16) and the portion of substrate 10 around the outer periphery of layer 11. Thus, N-type semiconductor layer 12 has a rectangular periphery (as shown in FIG. 3) which is larger than the rectangular periphery of layer 11.
P-type semiconductor substrate material 10 surrounds the periphery of N-type semiconductor layer 12 (when viewed as in FIG. 3). Layers 11 and 12 of N-type semiconductor material together comprise a large, single tub (well) of N-type semiconductor material in P-type substrate 10.
Field oxide layer 13 is deposited on the exposed upper surfaces of substrate 10 and N-type semiconductor layer 12 (as shown in FIG. 4), but not over the thick portion of layer 11 underlying contact M16. Layer 13 is not shown in FIG. 3, to allow the other layers to be depicted.
Then, multiple strips of polysilicon (e.g., the four parallel strips comprising polysilicon resistor portions RS1-RS10) are deposited on field oxide layer 13. Finally, a pattern of metal (having high electrical conductivity) is deposited on portions of the polysilicon material, on portions of the field oxide layer 13 between the polysilicon strips, and on the thick portion of N-type semiconductor layer 11, to implement metal contacts and connectors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, and M16 (best shown in FIG. 3). Metal contact M16 is coupled to output node Vout of FIG. 2. Metal contact M1 is coupled to node X (of FIG. 2) so that current can flow from contact M1 through contacts M2, M3, M4, and M5 to one end of polysilicon resistor strip RS1.
By implementing one tub of N-type semiconductor material (layers 11 and 12) in P-type substrate 10 and coupling the tub to output node Vout (via contact M16), the effect of resistor R.sub.c 's stray capacitance over field oxide layer 13 is reduced, thus allowing the amplifier to achieve faster output transient response without affecting its gain.
The FIG. 3 embodiment includes a layer of metal (M1-M4) over the left part of the polysilicon strip at the top of FIG. 3 for the following reason. It may be desired to deposit four identical, parallel polysilicon strips on field oxide 13, rather than three long strips and one short strip (e.g., because it is efficient to do so from a manufacturing standpoint), although the total length of all four strips exceeds the desired length of polysilicon material for implementing resistor R.sub.c. With four such identical polysilicon strips on the field oxide, the effective resistance of one of the polysilicon strips (i.e., the top strip in FIG. 3) is reduced by coating much of the strip with metal (i.e., to form a large contact comprising metal M1, M2, M3, M4, and M5, as shown in FIG. 3). Also, metal connectors M6-M14 (of FIG. 3) are deposited to short-circuit an end of each polysilicon strip with an end of another one of the strips (and to short-circuit adjoining portions of the three identical strips) to implement resistor R.sub.c with ten equal-length polysilicon resistor portions (i.e., equal-length portions RS1-RS10 of FIG. 3) connected together by metal.
Alternatively (in a variation on FIG. 3), three long polysilicon strips (i.e., strips identical to the three lower polysilicon strips of FIG. 3) and one short polysilicon strip (i.e., one just long enough to implement strip RS1 of FIG. 3) are deposited on field oxide 13. Small metal contact MS is then deposited at one end of the short polysilicon strip and contact MS is connected directly to node X (of FIG. 2). In such implementations, metal M1, M2, M3, and M4 are preferably omitted.
In other variations on the FIG. 3 embodiment, resistor R.sub.c is implemented with more than ten or less than ten polysilicon strips (and/or portions of polysilicon strips connected by metal) deposited on a field oxide layer over a single tub of N-type semiconductor material. The polysilicon strips (or portions of strips between metal connectors) can, but need not, have identical length and resistance. For example, resistor R.sub.c can be implemented as three portions of a single polysilicon strip (with a metal connector deposited between the central portion and the two end portions of the strip. For another example, resistor R.sub.c can be implemented as five parallel strips of polysilicon, with each strip partitioned into three portions (i.e., a total of fifteen polysilicon strip portions) and a metal connector between each pair of adjacent strip portions (i.e., a total of fourteen metal connectors).
As noted, the typical resistance of resistor R.sub.c is about 3400 Ohms (in FIGS. 1 and 2). To implement R.sub.c with this resistance, the total resistance of polysilicon strip portions RS1-RS10 of FIG. 3 should be 3400 Ohms. FIG. 5 is a schematic diagram of the circuit equivalent of the FIG. 3-4 implementation of resistor R.sub.c, with parameters chosen so that each of polysilicon strips RS1-RS10 has resistance 340.2 Ohms (so the total resistance of R.sub.c is 3402 Ohms). To allow convenient comparison of the FIG. 5 diagram to the below-discussed FIG. 11 diagram, FIG. 5 treats polysilicon strip RS2 of FIG. 3 as comprising two portions, denoted as RS2.sub.A and RS2.sub.B in FIG. 5, with portion RS2.sub.A being shorter than portion RS2.sub.B and thus having lower resistance (40.8 ohms) than portion RS2.sub.B (whose resistance is 299.4 ohms). Similarly, FIG. 5 treats each of polysilicon strips RS3-RS9 of FIG. 3 as comprising two portions (RS3.sub.A and RS3.sub.B, RS4.sub.A and RS4.sub.B, RS5.sub.A and RS5.sub.B, RS6.sub.A and RS6.sub.B, RS7.sub.A and RS7.sub.B, RS8.sub.A and RS8.sub.B, and RS9.sub.A and RS9.sub.B, respectively). FIG. 5 models each resistor portion (which comprises an area of N-type semiconductor material coupled to output node Vout, under an area of polysilicon, and a volume of insulating field oxide therebetween) as a capacitor. The value (indicated in FIG. 3) of the capacitance of each such capacitor assumes a typical thickness (9500 angstroms) of field oxide layer 13. FIG. 5 models N-type layers 11 and 12 (layer 11 being coupled to output node Vout via contact M16) and P-type substrate 10 (coupled to ground as shown in FIG. 4) as a diode D1. Nodes X and Y of FIG. 5 correspond to nodes X and Y of FIG. 2.
The advantage of implementing resistor R.sub.c as in FIGS. 3 and 4 (rather than as in FIG. 1) will be apparent from comparing FIGS. 6 and 7 with FIG. 8. FIG. 6 is a graph representing the output potential (Vout) of the FIG. 1 circuit as a function of time, in response to a square wave input potential Vin (having period 100 nsec), for each of three values of stray capacitance due to three values of the thickness of the field oxide layer on which resistor R.sub.c is formed. FIG. 8 is a graph representing the output potential (Vout) of the FIG. 2 circuit as a function of time, in response to a square wave input potential Vin (having period 100 nsec), for each of the same three values of the thickness of the field oxide layer on which resistor R.sub.c is formed (assuming the FIG. 3-4 implementation of resistor R.sub.c). FIG. 6 assumes that resistor R.sub.c is implemented as in FIGS. 3-4, but with layers 11 and 12 and metal contact M16 omitted, and with field oxide layer 13 deposited directly on the P-type semiconductor material comprising substrate 10. Thus, FIG. 6 assumes that there is no tub of N-type semiconductor material under the series-connected polysilicon strips comprising resistor R.sub.c.
Curve 31 of FIG. 6 assumes a typical thickness (9500 angstroms) for the field oxide layer. Curve 30 of FIG. 6 assumes that the field oxide layer has twice the typical thickness, and curve 32 of FIG. 6 assumes that the field oxide layer has thickness equal to 67% of the typical thickness.
Because the implementation of resistor R.sub.c of FIG. 1 (which results in the FIG. 6 curves) has a large stray capacitance associated with each resistor portion (each resistor portion comprising an area of grounded substrate material, under an area of polysilicon, with a volume of field oxide therebetween), the leading and trailing edges of each of curves 30, 31, and 32 of FIG. 6 exhibit sluggish rise and fall times.
Because the FIG. 3 implementation of resistor R.sub.c of FIG. 2 (which results in the FIG. 8 curves) employs bootstrapping (each resistor portion comprises an area of N-type semiconductor material coupled to the output node Vout, under an area of polysilicon, with a volume of field oxide therebetween) the effect of resistor R.sub.c 's stray capacitance over the field oxide layer is reduced, causing the leading and trailing edges of each of curves 40, 41, and 42 of FIG. 8 to have shorter rise and fall times than do the leading and trailing edges of curves 30, 31, and 32 of FIG. 6. However, the leading and trailing edges of each of curves 40, 41, and 42 of FIG. 8 exhibit large overshoot and large differences in overshoot from curve to curve which are not acceptable for many amplifier applications. The present invention eliminates this problem.
Also, the slope (and overshoot) of the leading and trailing edges of both FIG. 6 and FIG. 8 undesirably depend on the thickness of the field oxide layer on which the polysilicon resistor strips are deposited. As most apparent from FIG. 7 (which is an enlarged detail of a portion of each of curves 30, 31, and 32 of FIG. 6), the overshoot value of curve 30 (the amount by which the maximum value of the curve exceeds the upper plateau to which each cycle of the curve settles) which is associated with a relatively thick field oxide layer, and the leading edge slope of curve 30, are greater than the overshoot value and leading edge slope of curve 31 (associated with a thinner field oxide layer), and much greater than the overshoot value and leading edge slope of curve 32 (associated with an even thinner field oxide layer). This dependence on field oxide layer thickness (apparent from FIGS. 6 and 7) is due to the time constant associated with resistor R.sub.c and the stray capacitance of this resistor to the semiconductor substrate. Decrease in the thickness of the field oxide layer results in larger stray capacitance to ground, and thus smaller slope and smaller overshoot of the leading and trailing edges.
On the other hand, the phenomenon apparent from FIG. 8 has another cause: decrease in the thickness of the field oxide layer results in larger stray capacitance to the output node V.sub.out, and thus more positive feedback from V.sub.out to R.sub.c through this stray capacitance, and thus greater slope and greater overshoot of the leading and trailing edges. The overshoot value and leading edge slope of curve 40 (associated with a relatively thin field oxide layer) are greater than the overshoot value and leading edge slope of curve 41 (associated with a thicker field oxide layer), and much greater than the overshoot value and leading edge slope of curve 42 (associated with an even thicker field oxide layer).
Until the present invention, it had not been appreciated that the structure of conventional implementations of the gain-setting resistor R.sub.c of a high-speed amplifier of the type shown in FIGS. 1 and 2 strongly affects the amplifier's response time (the speed at which it responds to a change in the input signal) and the overshoot values of the amplifier's response to a time varying input in the manner discussed above. Nor had it been known how to implement a gain-setting resistor in an amplifier of this type to overcome the noted problems with (and limitations of) conventional implementations of such an amplifier.